TSMC Reveals Advanced CoWoS Roadmap: 48x More Compute and 34x Greater Bandwidth by 2029
Key Takeaways
- ▸TSMC will deliver 14+ reticle-sized SiPs with up to 24 HBM5E stacks by 2029, enabling 48x more compute transistors and 34x more memory bandwidth than 2024 systems
- ▸Advanced packaging (CoWoS and SoIC technologies) is replacing traditional Moore's Law transistor scaling as the primary growth engine for AI compute
- ▸Future packages will be massive (roughly 12,020 mm² for 14-reticle designs) and will require exotic cooling solutions and significant server redesigns
Summary
At the North American Technology Symposium 2026, TSMC unveiled an updated CoWoS (Chip-on-Wafer-on-Substrate) packaging roadmap that represents a significant leap in AI accelerator capabilities. The company plans to produce 14-reticle and larger System-in-Packages (SiPs) by 2029, capable of supporting up to 24 HBM5E memory stacks—compared to today's 5.5-reticle packages with 12 HBM3E/HBM4 stacks. This roadmap demonstrates that advanced packaging technology, rather than traditional lithography scaling, has become the primary driver for semiconductor performance improvements to meet the insatiable compute and memory bandwidth demands of AI applications.
TSMC's roadmap includes several key milestones: current production of 5.5-reticle CoWoS packages with over 98% yield, a 2027 introduction of 9.5-reticle interposers with 12 HBM5 stacks, a 2028 target of 14-reticle packages supporting 20 3D-stacked chiplets and 20 HBM5 modules, and eventual 14+-reticle packages by 2029. These massive packages—physically the size of a small plate—will enable systems with 48x more compute transistors and 34x greater memory bandwidth compared to 2024 multi-chiplet designs, fundamentally shifting how AI servers are architected and requiring new cooling solutions and power delivery infrastructure.
- TSMC's current 5.5-reticle CoWoS production already achieves over 98% yields, validating the technology for near-term deployment
