UALink Consortium Releases Specification 2.0 with In-Network Compute and Chiplet Support
Key Takeaways
- ▸In-network compute reduces latency and bandwidth while improving scaling efficiency for distributed AI training and inference workloads
- ▸Separation of link and physical layers enables independent evolution of interconnect speeds without disrupting the entire standard
- ▸New chiplet specification prevents vendor lock-in and allows accelerator designers to build modular systems from multiple suppliers
Summary
The UALink Consortium released UALink Common Specification 2.0, a major update to the AI accelerator interconnect standard less than a year after its initial release in April 2025. The new specification introduces in-network compute capabilities that enable distributed training and inference to operate more efficiently by allowing computation and communication to happen directly within the interconnect fabric, reducing latency and bandwidth requirements. The update also splits the link layer from the physical layer, providing flexibility for independent updates and support for faster transmission speeds without disrupting the entire stack.
Additionally, UALink 2.0 adds a chiplet specification developed in collaboration with the UCIe (Universal Chiplet Interconnect Express) consortium. This advancement allows accelerator manufacturers to build modular, chiplet-based systems without being locked into a single vendor's interconnect stack. The specification also incorporates standardized protocols, modeling, and APIs for improved manageability with centralized control and management planes, making it easier for the industry to implement UALink solutions across diverse multi-workload environments.
- UALink positioned as complementary to existing standards (PCIe, Ethernet, CXL, UCIe) while addressing accelerator-specific interconnect needs
