Veryl 0.20.0 Adds Logic Synthesis and Type Inference to Hardware Description Language
Key Takeaways
- ▸Logic synthesis support enables developers to evaluate gate-level area, timing, and power metrics directly within the Veryl toolchain using SKY130, ASAP7, GF180MCU, and IHP SG13G2 process technologies
- ▸Type inference reduces boilerplate by automatically inferring types for variable declarations from right-hand side expressions or first assignments
- ▸SystemVerilog-to-Veryl translator facilitates migration of existing hardware designs, lowering adoption barriers for designers familiar with traditional HDLs
Summary
Veryl, an open-source hardware description language (HDL) designed as an alternative to SystemVerilog, has released version 0.20.0 with significant new capabilities. The release introduces logic synthesis support via the veryl synth command, which performs gate-level synthesis directly from the toolchain and reports area, timing, and power consumption for designs. A new SystemVerilog-to-Veryl translator enables incremental migration of existing hardware designs.
The language itself gains enhanced type inference for let, const, and var declarations, allowing developers to omit type annotations when the type can be inferred from assignment. A new gen declaration enables generic modules to compute derived types that can be passed as generic arguments to inner instances. The release also refines syntax for loop iterators and testbench assertions, with improved debugging output on assertion failures.
Editorial Opinion
Veryl's 0.20.0 release demonstrates mature language design by balancing expressiveness with pragmatism—removing unnecessary type annotations while adding synthesis-aware tooling. The inclusion of synthesis metrics directly in the development flow could accelerate hardware design iteration, particularly for open-source silicon projects and academic research.
